PROJECTS
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Design and Implementation of a top level test access port for logic BIST instrument access
MAJOR_PROJECT.pdf
o Designed a comprehensive Top-Level Test Access Port (TAP) for testing IP cores within SoC designs, enabling efficient and robust verification of multiple functional units.
o Adopted a modular, hierarchical testing framework using System Verilog, covering requirements analysis, architecture design, implementation, and verification.
o Developed TAP controller, test data multiplexing systems, and protocol-based communication interfaces; ensured standardized IP integration and advanced test data management.
o Thoroughly tested and simulated all components, confirming the architecture's reliability for simultaneous multi-IP testing with high data integrity and timing accuracy.
o fully integrated all components, design and incorporate UART protocol for enhanced communication, and validate the system using advanced industry tools and methodologies
Design and FPGA Implementation of a UART module
o Designed and implemented a Universal Asynchronous Receiver Transmitter (UART) module with transmitter, receiver, and baud rate generator using Verilog HDL.
o Performed functional simulation and verification using Xilinx Vivaldo 2020.2.
o Implemented and tested the design on Zedboard FPGA using onboard switches and LEDs for data transmission and reception
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